In the fabrication of ultra-large scale-integration (ULSI) circuits, vertical stacking, or integration, of metal wiring circuits, or metal layers, to form multilevel interconnection has become an efficient way to increase circuit performance and increase the functional complexity of the circuits. Electrical connections between adjacent metal layers are achieved by an interconnect layer provided for each metal layer (intra-layer connection), and one or more via holes that are formed through the sandwiched dielectric layer and connect two adjacent interconnect layers (inter-layer connection).
The interconnect layer typically comprises a plurality of very thin and long aluminum-based wires, or interconnects. Due to the large difference in the thermal expansion coefficients between the aluminum interconnect and the silicon substrate, a so-called stress-induced migration often occurs when the wafer is subject to a rapid temperature ramp rate, which could go up or down. Under large tensile stresses, wherein aluminum atoms are pulled away from the interconnect, voids could occur, resulting in a substantially increased line resistence or, in the worst case, even a total severance of the interconnect. On the other hand, when compressive stresses are present, bulges could be formed which could fracture the dielectric or passivation layer above the interconnect and cause circuit shorting to occur.
U.S. Pat. No. 5,439,731 disclosed a method of manufacturing a semiconductor device. The '731 patent recognized the problems associated with the rapid temperature ramp rate in fabricating semiconductor devices and proposed a method which slows down the ramp rate. Thus, the '731 patent provides that, when a film is formed by depositing Al or Al alloy on a semiconductor substrate formed with a hole in accordance with sputtering, the film is formed at an initial stage under the condition that the semiconductor substrate is kept heated at 180.degree. C. or lower. After the initial stage, the film is formed in a stepwise manner by stepwise changing the heating temperature of the semiconductor substrate in at least two stages under the condition that the semiconductor substrate is kept heated at a temperature of approximately 460.degree. C. or higher.
U.S. Pat. No. 5,252,382 disclosed an interconnect structure which eliminates or reduces stress migration in the interconnect. The interconnect structure comprises: (a) a first dielectric layer; (b) a metal interconnect formed over the first dielectric layer and forming a first interface therewith; and (c) a second dielectric layer formed over the metal interconnect and forming a second interface therewith. The main element of the '382 invention is that the first and second interfaces are patterned to have regions of good adhesion and regions of substantially no adhesion.
U.S. Pat. No. 5,439,731, which was invented by the same inventor as the '382 patent, discloses another metal interconnect structure which comprises: (a) an insulating substrate; (b) a first plurality of spaced, electrically conductive metal segments formed on the substrate, each having a pair of vertical sides and being separated by a plurality of corresponding gaps between adjacent ones of the first plurality of segments; (c) a refractory metal back-up layer conformally formed over the first plurality of electrically conductive metal segments and the plurality of gaps, wherein the back-up layer includes a plurality of vertical portions adjacent each the vertical side of the first plurality of segments, and a plurality of troughs are formed above the backup layer and the gaps between adjacent ones of the vertical portions; and (d) a second plurality of electrically conductive metal segments formed in the troughs between and contacting the vertical portions.
The '731 patent further provides that the first and second plurality of electrically conductive segments and the plurality of vertical portions of the refractory metal back-up layer form a metal interconnect, and that each segment in the first and second plurality of segments has a length which minimizes stress migration and electromigration damage by limiting the amount of vacancies for voids and atoms for hillocks, and each the vertical portion of the refractory metal back-up layer has a width which enables the vertical portion to block atomic transport between adjacent ones of the first and second plurality of electrically conductive segments, while at the same time minimizing electrical resistance through each the vertical portion.
The above references illustrate some examples of the stress-induced migration related problems that are facing the semiconductor industry as the size of the semiconductors becomes increasingly smaller. Most of the improvements disclosed in the prior art references regarding metal interconnects involve relatively complicated additional steps; they are also very limited in scope.
Another problem that has been observed relating to the stress-induced migration of aluminum atoms is the via failure. Two types of via failures have been observed, one is associated with the voiding in metal interconnect lines, due to the stress induced migration, of aluminum atoms into holes that may be present in the vias, resulting in circuit failure. This type of circuit failure has been reported by Matsukawa, et al, in an article entitled: "A New Model for Via Failure Mechanism of Stress-Induced Migration Voiding of Al-Plug of Via on Al-Fill Process in Multilevel Interconnect Processes," Jun. 10-12, 1997 VMIC Conference, 1997 ISMIC- 107/97/0479(c).
The other type of via failure was observed by the inventor of the present invention. This type of via failure occurred typically only during the fabrication of very small size semiconductor devices containing very long and very fine interconnect lines, and wherein the via holes are, because of their fine size, not completely filled with a tungsten plug. More specifically, the inventor of the present invention observed that when the interconnect was long enough and thin enough, the tri-axial stress, which is inversely proportional to the thickness of the interconnect, would become so strong that substantial amounts of aluminum atoms or defects could be pushed into the via hole causing the via to protrude from its open end. This can cause severe problems in patterning the subsequent metal layer. None of the prior art methods have addressed or even identified this kind of problem.